DFM&Y 2006 - Call for Participation

CALL FOR PARTICIPATION

Scope -- Workshop At A Glance -- Committee Members -- Program -- Additional Information

Scope

Increased manufacturing susceptibility in today's nanometer technologies requires up to date solutions for yield optimization. In fact, designing an SoC for manufacturability and yield aims at improving the manufacturing process and consequently its yield by enhancing communications across the design-manufacturing interface. A wide range of Design-for-Manufacturability (DFM) and Design-for-Yield (DFY) methodologies and tools are proposed today. Some of which are leveraged during the back-end design stages, and others have post-design utilization, from lithography up to wafer sort, packaging, final test and failure analysis. DFM and DFY can dramatically impact the business performance of chip manufacturers. It can also significantly affect age-old chip design flows. Using DFM and DFY solutions is an investment and thus choosing the most cost effective one(s) requires trade-off analysis. The workshop analyzes this key trend and its challenges, and provides an opportunity to discuss a range of DFM and DFY solutions for today's SoC designs.

Workshop At A Glance

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Thursday -- Friday

THURSDAY, OCTOBER 26
2:00 pm - 5:00 pm	Registration
4:00 pm - 5:00 pm	Opening Session
5:00 pm - 7:00 pm	Session 1: DFM&Y and Test
7:00 pm - 9:00 pm	Evening Reception
FRIDAY, OCTOBER 27
7:00 am - 8:00 am	Continental Breakfast
8:00 am - 10:00 am	Session 2: Context and Perspectives on DFM&Y
10:00 am - 10:30 am	Break
10:30 am - 12:30 pm	Session 3: DFM&Y and Physical Design
12:30 pm - 1:30 pm	Lunch
1:30 pm - 3:30 pm	Session 4: Topics in DFM&Y
3:30 pm - 5:00 pm	Session 5: Panel - "What Will Make or Break DFM&Y"

Committee Members

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WORKSHOP COMMITTEE
General Chair
Yervant Zorian
Virage Logic

Co-General Chair
Juan-Antonio Carballo
IBM

Program Chair
Andrew B. Kahng
Blaze DFM

Publication
A. Ivanov
Univ British Columbia

Panels
R. Camposano
Synopsys

Finance
R. Aitken
ARM

Publicity
D. Gizopoulos
Univ Piraeus

PROGRAM COMMITTEE
D. Appello, ST Microelectronics
C. Bittlestone, Texas Instruments
A. Gattiker, IBM
K.S. Kim, Intel
F. Kurdahi, UC Irvine
H. Lee, Magma
A. Markosian, Ponte Solutions
D. Maynard, IBM
C. Metra, Univ of Bologna
S. Muddu, UC San Diego
M. Murakata, STARC
S. Nassif, IBM
M. Nicolaidis,TIMA
N. Ns, Texas Instruments
M. Orshansky, Univ of Texas
V. Pitchumani, Intel
J.M. Portal, Univ of Marseille
P. Prinetto, Pol. di Torino
R. Radojcic, Qualcomm
J. Rey, Mentor Graphics
K. Roy, Purdue Univ
A. Singh, Auburn Univ
D. Sylvester, Univ of Michigan
V. Vardanian, Virage Logic
B. Vermeulen, Philips
D.M.H. Walker, Texas A&M Univ
S. Wigley, LTX
C-W. Wu, National Tsing Hua Univ
H-J. Wunderlich, Univ of Stuttgart
G. Yeric, Synopsys

Workshop Program

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Thursday -- Friday

THURSDAY, OCTOBER 26
2:00 pm - 5:00 pm	Registration
4:00 pm - 5:00 pm	Opening Session Welcoming Remarks General Chair Y. Zorian, Virage Logic Program Chair A. B. Kahng, UCSD Keynote Address "DFM&Y: Whose Problem is it Anyway?" N. NS, Texas Instruments
5:00 pm - 7:00 pm	Session 1: DFM&Y and Test Session Chair Andre Ivanov Univeristy of British Columbia 1.1 Test Structures for Process and Product Performances Evaluation Fabrice Rigaud, J.M. Portal, H. Aziza, D. Nee, J. Vast and C. Auricchio, ST Microlelectronics, U. of Marseille 1.2 Hardware Debug Infrastructure for Soc Featuring Embedded Configurable Logic Stefano Pucillo, Lorenzo Cali and Stefania Stucchi, STMicroelectronics 1.3 Test Chip Methods for Successful DFM Greg Yeric, Synopsys 1.4 Accounting for Chip Yield at the Application Level Fadi Kurdahi, Ahmed Eltawil, Kang Yi, Young-Hwan Park, Amin Khajeh Djahromi, and Yervant Zorian, UC Irvine and Virage Logic Wrap up Discussion
7:00 pm - 9:00 pm	Evening Reception
FRIDAY, OCTOBER 27
7:00 am - 8:00 am	Continental Breakfast
8:00 am - 10:00 am	Session 2: Context and Perspectives on DFM&Y Session Chair Julie Segal Spanion 2.1 DFM: State and Directions Sunit Rikhi, Intel 2.2 Using Test as the Ultimate Measure of DFM Effectiveness Bob Madge, LSI Logic 2.3 Advances on Proactive DFM Experiences David Appello, ST Microelectronics 2.4 DFM&Y Research and Development topics in STARC Masami Murakata, STARC
10:00 am - 10:30 am	Break
10:30 am - 12:30 pm	Session 3: DFM&Y and Physical Design Session Chair Kazumi Hatayama STARC 3.1 Lithography- and CMP-Aware Routing David Pan, UT Austin 3.2 Manufacturing Models & Implementation Technology Matt Liberty, Cadence 3.3 Manufacturability-Driven Physical Synthesis Patrick Groeneveld, Magma 3.4 The Marriage of DFM and Physical Design: Can It Work? Joe Hutt, Pyxis 3.5 Lithography-Aware Physical Design: Challenges and Opportunities Xinying Zhang, Synopsys
12:30 pm - 1:30 pm	Lunch
1:30 pm - 3:30 pm	Session 4: Topics in DFM&Y Session Chair Rene Segers NXP 4.1 Simple and Accurate Models of Capacitance Increment Due to Metal Fill, Youngmin Kim, U. Michigan 4.2 A Modeling Technique for Non-Rectangular Gates for Static Timing Analysis Shayak Banerjee, UT Austin 4.3 A Yield Enhancement Technique for Standard Cell Libraries Ara Aslyan, Ponte Solutions 4.4 Fast Dual Graph-Based Hotspot Detection Chul-Hong Park, UC San Diego 4.5 DFM Framework for Dynamic Yield Optimization Fedor Pikus, Mentor Graphics 4.6 Yield Prediction Using Via Distribution Model Takumi Uezono, Tokyo Institute of Technology
3:30 pm - 5:00 pm	Session 5: Panel - "What Will Make or Break DFM&Y" Co-Organized with: IEEE Design & Test of Computer Moderator Gary Smith Gartner Dataquest Panelists: Rob Aitken, ARM Juan-Antonio Carballo, IBM Andrew Kahng, UC San Diego Ara Markosian, Ponte Solutions Masami Murakata, STARC David Overhauser, Overhauser-Li Consultancy David Pan, UT Austin Yervant Zorian, Virage Logic

Additional Information

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WORKSHOP LOCATION
DFM&Y 2006 will be held at Santa Clara Convention Center, Santa Clara, California, USA, October 26 - 27, 2006, immediately following ITC 2006 (www.itctestweek.org).

REGISTRATION
All Workshop participants require registration. Please register using the ITC 2006 Registration Forms.

SPECIAL ISSUE
The best contributions of DFM&Y 2006 will appear in a Special Issue of JETTA (the Journal of Electronic Testing: Theory and Applications).

INFORMATION CONTACTS
For more information on the Workshop, please contact:
Yervant ZORIAN
y.zorian@computer.org

Website
http://www.unipi.gr/dfmy

TTTC Office:
IEEE TTTC
1474 Freeman Dr
Amissville, VA 20106 USA
Tel: +1-540-937-8280
Fax: +1-540-937-7848
Email: tttc@computer.org

For more information, visit us on the web at: http://www.unipi.gr/dfmy

The 1st IEEE International Workshop on Design for Manufacturability & Yield (DFM&Y 2006) is sponsored by the IEEE Computer Society Test Technology Technical Council, in Cooperation with CEDA - IEEE Council on Electronic Design Automation and in Conjunction with Test Week / Interntional Test Conference 2006 (ITC 06).